The present invention relates to a circuit which allows processors to read or write data in dual-data formats.
Two types of byte ordering for processing data include the big endian byte ordering and the little endian byte ordering, as shown in FIG. 1. In big endian format 100, the order of bytes in a word is such that the most significant byte or digits are placed left-most in the word structure, the way humans deal with normal arithmetic. In comparison, little endian format 110 places the least significant byte or digits leftmost in the word structure. With the little endian format, the word structure is set-up for the required processing order, since numbers are calculated by a processor starting with the least significant (left-most) digits.
Because of the existence of the two endian byte ordering formats, there are two possible endian situations when running programs in a mixed endian processing environment. The first possibility is where the internal endian format of the processor matches that of the software data. In this case, no conversion of the data is required, since the data bytes can be read directly by the processor. The second possibility is where the internal endian format of the processor does not match that of the software data. In this latter case, a series of shifts and swaps are required to transform the data into the endian format to match that of the processor, because processors only read data in their own endian format. In particular, the processor must store the data in a temporary storage and perform a series of shifts and swaps under software control to reconfigure the data to the particular endian format used by it. This software manipulation consumes valuable memory space and time.
Accordingly, a need exists to facilitate conversion of data between particular endian formats.
A method consistent with the present invention reconfigures data for communication between processors and a memory. The method includes receiving a plurality of bytes in a particular dual-data format, and receiving a control signal set to a first state if the processors and the memory are in the same dual-data format and set to a second state if the processors and the memory are in a different dual-data format. The method also includes selectively reconfiguring the bytes based upon the control signal, including transmitting the data in the particular dual-data format if the control signal is set to the first state and reconfiguring the particular dual-data format of the bytes if the control signal is set to the second state.
A first interface consistent with the present invention transmits and selectively reconfigures data between processors and a memory. The interface includes a data bus for receiving a plurality of bytes in a particular dual-data format, and a control terminal for receiving a control signal which is set to a first state if the processors and the memory are in the same dual-data format and set to a second state if the processors and the memory are in a different dual-data format. The interface also includes control logic, coupled to the data bus and the control terminal, that transmits the data in the particular dual-data format if the control signal is set to the first state and reconfigures the particular dual-data format of the bytes if the control signal is set to the second state.
A second interface consistent with the present invention transmits and selectively reconfigures data between processors and a memory. The interface includes a first data bus for receiving bytes, a second data bus for outputting bytes, and a control terminal for receiving a control signal based upon a particular dual-data format of the received bytes. The interface also includes a logic circuit coupled to the first data bus, the second data bus, and the control terminal. The logic circuit receives the bytes from the first data bus, selectively reconfigures the particular dual-data format of the received bytes based upon the control signal, and outputs the selectively reconfigured bytes on the second bus.